Synchronous DRAM modules with multiple clock out signals

ABSTRACT

Additional clock-outs are included on DRAMs in a multiple Dual In-Line Module Memory (DIMM) system having DRAMs of different data widths. The additional clock-outs balance the loads seen by the DRAM clock-out and data-out, thereby reducing signal skew between the DRAM data and clock lines. Additionally, in a second embodiment, every other clock line in a series of DRAMs comprising a DIMM are left unconnected. The data from the non connected DRAMs is clocked using the clock line of its neighbor.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of data storage andretrieval, and in particular, data storage and retrieval fromsemiconductor memories.

[0003] 2. Background of the Invention

[0004] In today's computer environment, DRAMs are one of the dominantmemory technologies. DRAMs are the preferred choice for large mainmemories because they are inexpensive, fast and consume little power.

[0005] DRAMs are typically manufactured in discrete semiconductorpackages having different input/output (I/O) data widths of, forexample, four, eight, or sixteen output data bits, and are thus referredto as x4, x8, or x16 DRAMs, respectively. The number of data bits that acomputer can simultaneously address and manipulate, i.e., the computerbus width, is typically much larger than that commonly available withDRAMs. For example, computers produced today may have bus widths of 32,64, or 128 bits. To accommodate these bus widths, groups of DRAMs arepackaged together to form single memory modules, for example, DIMMs(Dual In-line Memory Modules) or SIMMs (Single In-line Memory Modules).

[0006]FIG. 1 is a block diagram showing a proposed 64 bit DIMM includingeight x8 DRAMs 108, 110, 112, 114, 116, 118, 120 and 122. IC chipset 102latches data as one sixty-four bit word from/to DRAMs 108 through 122and then, when appropriate, transmits/receives the sixty-four bit wordon computer bus 124. Central Processing Unit (CPU) 125 is connected tobus 124. Computer bus 124 couples the memory system shown to othersections of the computer. Each DRAM 108-122 includes an 8 bit data out(DQ) bus 106 and a one bit clock-out 104. For clarity, the detailedstructure of the DIMM address and enable lines are not shown.

[0007] The data from each DRAM 108-122 is transferred to/from IC chipset102 synchronously. That is, when DRAM 108 outputs data to its data bus106, it simultaneously raises its clock-out line 104. IC chipset 102latches the received data from data bus 106 when it detects the raisedclock signal.

[0008] Load capacitance and signal line length introduce propagationdelays in any signal transmitted from the DRAMs 108 through 122 to ICchipset 102. Accordingly, although data may be transmittedsimultaneously from DRAMs 122 and 108, data transmitted from DRAM 122can arrive at IC chipset 102 before data from DRAM 108. In thissituation, to receive data from all the DRAMs 108 through 122 in theabsence of clock-out signals, IC chipset 102 must wait for thepropagation delay associated with each DRAM to resolve itself beforeinitiating latching of all 64 bits. As a result, a long waiting periodis required which undesirably restricts the maximum frequency at whichthe DIMM 100 can operate.

[0009] A separate clock line has been proposed on each DRAM, as shown inFIG. 1, in order to overcome the above-described problem. Although theeight data bits from DRAM 108 will experience a different propagationdelay than the eight data bits from DRAM 122, for example, the DRAM datais transmitted simultaneously with its own clock signal. Because thedata lines and clock lines from, for example, DRAM 108, see the samecapacitive load and signal line length, the propagation delays areapproximately the same (i.e., the lines are matched), and the clock anddata signals therefore arrive simultaneously. This allows the IC chipset102 to latch the data received from each of DRAMs 108-122 in response tothe received clock signal, thereby minimizing the delay encountered withthe DIMMs discussed above.

[0010] Consumers in the computer industry desire a modular, easilyupgradeable memory. To meet this demand, manufacturers have developedmodular memory systems which allow additional DIMMs to be added.

[0011]FIG. 2 is a block diagram of a memory system illustrating a memorysystem constructed from multiple DIMMs. DIMM 200 includes eight x8 DRAMs206 through 213 and DIMM 202 has four x16 DRAMs 214 through 217. Tosimplify FIG. 2, only eight-bit data bus lines 220 and 221 coupling thedata outputs of DRAMs 206, 207, and 214 to data path IC 204 are shown.Although not shown, similar data buses connect DRAM groups 208, 209, and215; 210, 211, and 216; and 212, 213, and 217. DIMM 200 has eightclock-outs connected to corresponding clock lines, one for each DRAM 206through 213. The clock lines from DRAMs 206 and 207 are illustrativelylabeled as lines 224 and 225, respectively. DIMM 202 has fourclock-outs, so each one is connected to two clock lines from DIMM 200.For example, the clock output 223 of DRAM 214 is coupled to clock lines224 and 225. Likewise, the clock line 232 of DRAM 215 is connected toclock lines 226 and 227. Further, although not shown ir FIG. 2, DIMMs200 and 202 are connected to IC chipset 204 through a common addressbus. Additionally, IC chipset 204 couples DIMMs 200 and 202 to CPU 229through bus 228.

[0012] Occasionally, upgrade DIMMs purchased by the consumer are madefrom DRAMs of different data widths. As a result, one DIMM will havemore clock lines than the other. This is shown in FIG. 2, in which DIMM200 has eight clock lines and DIMM 202 has four clock lines. BecauseDRAMs 206 through 213 each have eight data lines, their respectiveclock-outs can be directly connected to the clock input of IC chipset204. Each clock line from the x16 DRAM, however, must be split andconnected in parallel to two x8 DRAM clock lines.

[0013] Splitting the clock lines from the x16 DRAMs 214 through 217solves the problem of having a different number of clock lines betweenDIMMs 200 and 202, but introduces a new problem: splitting the clockline from DRAMs 214 through 217 introduces additional capacitive loadsseen by the clock lines, but does not change the capacitive load seen bythe data lines. Thus, the load seen by the DRAM clock line is no longermatched to the load of its corresponding data line, thereby introducingdifferences in the signal propagation time (also called signal skew). Asexplained above, differences in the signal propagation time between theclock and data signals decrease the speed at which the memory system canoperate.

SUMMARY OF THE INVENTION

[0014] The advantages and purpose of the invention will be set forth inpart in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theadvantages and purpose of the invention wil be realized and attained bymeans of the elements and combinations particularly pointed out in theappended claims.

[0015] To attain the advantages and in accordance with the purpose ofthe invention, as embodied and broadly described herein, a dynamicrandom access memory (DRAM) arranged on a single integrated circuit isprovided. The DRAM has a plurality of clock outputs and a plurality ofdata outputs, a first portion of the plurality of clock outputs beingused to synchronously transfer a first portion of the plurality of dataoutputs.

[0016] Further, in another embodiment of the invention, a computermemory is provided which comprises a first memory module including afirst plurality of memory components, each of which having a pluralityof first data outputs and at least one timing signal output. A secondmemory module is further provided having a second plurality of memorycomponents, each of which having a plurality of second data outputs andat least one timing signal output, a number of the first plurality ofmemory components is different than a number of the second plurality ofmemory components. A plurality of data lines couples each of theplurality of first data outputs of each of the first plurality of memorycomponents to a respective one of each of the plurality of second dataoutputs of each of the second plurality of memory components. Inaddition, a plurality of timing signal lines couple each of the timingsignal outputs of each of the first plurality of memory components to arespective one of the timing signal outputs of the second plurality ofmemory components in a one-to-one corresponden Further, in accordancewith the present invention, a data processing system is provided whichcomprises a first memory module including a first plurality of memorycomponents, each of which having a plurality of first data outputs andat least a first timing signal output, and a second memory moduleincluding a second plurality of memory components, each of which havinga plurality of second data outputs and at least a second timing signaloutput, a number of said first plurality of memory components isdifferent than a number of said second plurality of memory components. Aplurality of data lines couple each of the plurality of first dataoutputs of each of the first plurality of memory components to arespective one of each of the plurality of second data outputs of eachof the second plurality of memory components. In addition, a datarouting circuit of the data processing system is coupled to each of theplurality of data lines and at least selected ones of the first andsecond timing signal outputs of the first and second memory modules,respectively, wherein a ratio of a number of first data outputs to anumber of first timing signal outputs coupled to the data routingcircuit equals a ratio of a number of second data outputs to a number ofsecond timing signal outputs coupled to the data routing circuit.

[0017] Moreover, a method of making a computer memory is providedcomprising the steps of: providing a first memory module having a firstplurality of memory components, each of which having a plurality offirst data outputs and at least one timing signal output; providing asecond memory module having a second plurality of memory components,each of which having a plurality of second data outputs and at least onetiming signal output, a number of the first plurality of memorycomponents is different than a number of said second plurality of memorycomponents; coupling each of the plurality of first data outputs of eachof said first plurality of memory components to a respective one of eachof the plurality of second data outputs of each of the second pluralityof memory components; and coupling each said at least one timing signaloutput of each of the first plurality of memory components to arespective one of the at least one timing signal output of the secondplurality of memory components, whereby the capacitive load associatedwith each of the first and second data outputs is equal to a capacitiveload associated with each of the first and second timing signal outputs.

[0018] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory only and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in andconstitute a part of this specification, illustrate several embodimentsof the invention and together with the description, serve to explain theprinciples of the invention. In the drawings,

[0020]FIG. 1 is a block diagram showing a 64 bit DIMM made from eight,x8 DRAMs;

[0021]FIG. 2 is a block diagram of a memory system illustrating aconventional memory system constructed from multiple DIMMs;

[0022]FIG. 3 is a block diagram of the first embodiment of the presentinvention;

[0023]FIG. 4 is a block diagram illustrating one exemplary variation onthe first embodiment.

[0024]FIG. 5 is a block diagram illustrating a second embodiment of thepresent invention.

[0025] Reference will now be made in detail to the present preferredexemplary embodiments of the invention, examples of which areillustrated in the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0026] This invention matches the data-out loads (i.e., impedanceassociated with capacitance, inductance, and resistance of the datalines) and the timing signal or clock-out loads of a multiple DIMMmemory system in which the clock output widths of the DRAMs (preferablySDRAMs) of one DIMM do not equal widths of the DRAMs of the second DIMM.DRAM load matching is accomplished by providing multiple clock outputson a DRAM, each clock output seeing a load matched to its correspondingdata output. By matching the data-out loads and the clock-out loads, theinvention reduces the difference in the propagation delays between aDRAM's clock-out and data-out, thus improving memory accessingperformance.

[0027] To illustrate the advantages achieved by the present invention, adiscussion of the capacitive loads in the proposed DIMM design and theDIMM of the present invention will be presented below.

[0028] Table 1 summarizes the loads seen by the DRAMs 206 through 217 ofthe conventional DIMMs shown in FIG. 2. TABLE 1 DIMMs Present in theSystem Data-Out Loads Clock-out Loads DIMM 200 ONLY 2 2 DIMM 202 ONLY 23 DIMMs 200 and 202 3 5

[0029] The first row of table 1 assumes only DIMM 200 is connected inthe memory system. In this case, the clock out of DRAM 206 would “see”two loads: its own output load and the receiving input load of line 224.Each data out line of DRAM 206 would see two loads also, one being itsown input/output load and the other being the corresponding input/outputload of DRAM 214 (connected via the corresponding data line from bus221). The system in the first row is balanced and will experience littlepropagation delay difference because the data-out loads and theclock-out loads are matched.

[0030] The second row of table 1 assumes only DIMM 202 is connected intothe memory system. With only DIMM 202 in the system, the clock out ofDRAM 214 sees 3 loads: its own, and the two input loads of IC chipset204 (connected to lines 224 and 225). In a manner similar to theprevious example, each data line would see two loads. In thisconfiguration, the system is unbalanced, such that the clock lines anddata lines will experience a measurable difference in their propagationdelay.

[0031] In the third row of table 1 the memory system is configured as isshown in FIG. 2, in which both DIMMs 200 and 202 are present. In thisconfiguration, the clock output for each DRAM sees five loads. The clockoutput 223 of DRAM 214, for example, sees: its own load, the clock outload of DRAM 206, the clock out load of DRAM 207, and the input loads ofIC chipset 204 (connected to lines 224 and 225). Each data output,however, sees three loads. For example, each data output of DRAM 214connected to bus 221 sees: its own load, the data input/output load ofDRAM 206, and the data input/output load of IC Chipset 204 (connectedvia a line on bus 221). Thus, in this configuration, each DRAM clock-outsees two more loads than its corresponding data-out, potentially causingsignificant timing problems due to signal skew.

[0032]FIG. 3 is a block diagram of the first embodiment of the presentinvention. Except for DIMM 302, the general structure of FIG. 3 issimilar to that of FIG. 2.

[0033] DIMM 300 preferably includes eight x8 DRAMs 306 through 313 andDIMM 302 includes four x16 DRAMs 314 through 317. Accordingly, thenumber of DRAM chips in DIMMs 300 and 302 is different. DIMM 300 shareseight clock lines 324, 325 and 335-340 with DIMM 302. Clock lines 324and 325, for example, are respectively connected to the clock outputs ofDRAMs 306 and 307 and extend to a IC chipset 304, a routing circuit,which couples DIMMs 300 and 302 to computer bus 341 and CPU 342. Theremaining clock lines 335-340 are respectively connected between theclock outputs of DRAMs 308-317 and to data path IC 304. Each of theclock outputs of DIMM 300 are coupled to a respective one of the clockoutputs of DIMM 302 in a one-to-one correspondence. In order to simplifyFIG. 3, only eight-bit data lines 320 and 321 are shown supplying datafrom DRAMs 306, 307 and 314 to datapath IC Chipset 304. Similar datalines supply data from DRAMs 307-313 and 315-317.

[0034] DIMM 302 preferably has eight clock-out lines; two from each DRAM314 through 317. Each clock output of DRAMs 314 through 317 isconstructed so that it sees the same delay, i.e., an equal delay in thesystem clock is experienced inside the DRAM by both the clock and thedata outputs.

[0035] Each of DRAMs 314 to 317 preferably include two clock outputs,each of which is respectively coupled to one of the clock outputs ofDRAMs 306-313. Accordingly, for example, first clock output line 323 ofDRAM 314 is coupled with clock output of DRAM 306 through clock outputline 324, while second clock output 350 of DRAM 314 is coupled to theclock output of DRAM 307 through clock output line 325. Similarly, clockoutput line 335 couples the clock output of DRAM 308 with a first clockoutput line 326 of DRAM 314, and clock output line 336 couple the secondclock output of DRAM 315 with the clock output of DRAM 309. The clockoutputs of DRAMs 310-313 and 316-317 are connected similarly, as shown.

[0036] As shown in table 2, the novel arrangement of the clock lines inthe present invention significantly improves the clock and data loadcharacteristics over the prior art. TABLE 2 DIMMs Present in the SystemDQ Loads Clock-out Loads DIMM 300 ONLY 2 2 DIMM 302 ONLY 2 2 DIMMs 300and 302 3 3

[0037] For example, when only DIMM 300 is present in the system, theembodiment in FIG. 3 has the same load characteristics as that of FIG.2. There are two data-out loads and two clock-out loads seen by eachdata-out and each clock-out, respectively. Thus, the loads are matchedand the system does not suffer from delays due to differences in signalpropagation delays.

[0038] When only DIMM 302 is connected in the first embodiment, eachdata out sees two loads. For example, each data out of DRAM 314 sees itsown input/output load and the input/output of IC chipset 304 (connectedvia one line on either bus 320 or 321). In addition, each clock-out inDRAM 314 also sees two loads. The first clock out of DRAM 314, forexample, sees its own load and the input load of IC chipset 304(connected via line 324), while the second clock output 350 sees its ownload and the input load of IC chipset 304 (connected via line 325).Therefore, as in the previous configuration, the loads are matched.

[0039] Moreover, when both DIMM 300 and 302 are present in the memorysystem the configuration causing the most propagation delay differencein the prior art, the data-out loads and the clock out loads are matchedat three each. Namely, the data-out of DRAM 314 corresponding to one oflines 321, for example, sees: its own load, the load of thecorresponding input/output pin of DRAM 306, and the load of thecorresponding input/output pin of IC chipset 304 (connected via data outline 321). The first clock out of DRAM 314 sees: its own load, thecorresponding load of DRAM 306, and the corresponding input load of ICchipset 304; and the second clock sees its own load, the correspondingclock output load of DRAM 307 and the input load of IC chipset 304.Further, the clock output of DRAM 307, for example, also sees threeloads. Thus, each clock output and each data output sees threecapacitive loads. As such, the data and clock signals output from DIMMs300 and 302 have the same delay, thereby eliminating the skewencountered by the prior art memory systems. Thus, the ratio of thenumber of clock outs to DQs of DIMM 300 (i.e., 1:8) equals the ratio ofclock outs to DQ of DIMM 302 (also 1:8). Accordingly, as noted above,the capacitive loads seen by each DQ is the same as that seen by eachclock out.

[0040] Although the preferred embodiment was described with two DIMMsusing x8 DRAMs and x16 DRAMs, the invention is not limited to thisconfiguration. In particular, the present invention can be generallyapplied to three or more DIMMs using two or more DRAM widths. FIG. 4 isa block diagram illustrating one exemplary variation on the firstembodiment. Alternatively, the present invention is applicable to asingle module.

[0041] In FIG. 4, DIMM 400 includes four x4 DRAMs, 401 through 404; DIMM410 is comprised of two x8 DRAMs, 411 and 412; and DIMM 420 is comprisedof one x16 DRAM, 421. Clock lines 430 and data buses 440 connect theDlMMs to the system IC chipset. As shown in the figure, two clock outlines emanate from the DRAMs 411, 412; four clock-out lines emanate fromDRAM 421, and one clock-out line emanates from each of DRAMs 401 through404. Correspondingly, each DIMM 400, 410, and 420 has four clock-outs.Thus, each clock out sees loads from three pins and a load due to theinterconnecting clock line. Similarly, each data-out line sees loadsfrom three pins and a load due to the interconnecting data line.

[0042]FIG. 5 is a block diagram illustrating a second embodiment of thepresent invention. FIG. 5 is similar to FIG. 2, except that in FIG. 5,DIMM 500 comprises sixteen x4 DRAMs 501 through 516 instead of eight x8DRAMs. Each four bit data-out bus 530 from DRAM 501 through 516 isconnected in parallel with four bits from DRAMs 521 through 524 to formone sixteen-bit-bus per DRAM 521 through 524. For the sake of clarity,not all the DQ lines are shown.

[0043] According to the embodiment shown in FIG. 5, each x16 DRAM hastwo clock-outs. Each clock out from the x16 DRAMs is connected to theclock out of every other x4 DRAM (clock-outs 502, 504, 506, 508, 510,512, 514, and 516). The clock-outs of DRAMs 501, 503, 505, 507, 509,511, 513, and 515 are not connected (N/C).

[0044] In operation, DRAMs 501 and 502 transmit and receive datasynchronized to the clock signal from DRAM 502. Although there may besome clock skew between the data of DRAM 501 and the clock of DRAM 502,because the DRAM chips 501 and 502 are of the same design and arepositioned physically close to one another, the clock skew is minimal(e.g., better than the extreme case of using only one clock out for thismodule) and well within tolerable system limits.

[0045] This embodiment is advantageous because DIMMs constructed withx16 DRAMs having only two clock-outs are rendered compatible with DIMMsconstructed with either x8 or x4 DRAMs without excessive system delay.

[0046] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the present inventionwithout departing from the scope or spirit of the invention.

[0047] Other embodiments of the invention will be apparent to thoseskilled in the art from consideration of the specification and practiceof the invention disclosed herein. It is intended that the specificationand examples be considered as exemplary only, with the true scope andspirit of the invention being indicated by the following claims.

What is claimed is:
 1. A computer memory comprising: a first memorymodule including a first plurality of memory components, each of whichhaving a plurality of first data outputs and at least one timing signaloutput; a second memory module including a second plurality of memorycomponents, each of which having a plurality of second data outputs andat least one timing signal output, a number of said first plurality ofmemory components is different than a number of said second plurality ofmemory components; a plurality of data lines coupling each of saidplurality of first data outputs of each of said first plurality ofmemory components to a respective one of each of said plurality ofsecond data outputs of each of said second plurality of memorycomponents; and a plurality of timing signal lines coupling each of saidat least one timing signal output of each of said first plurality ofmemory components to a respective one of said at least one timing signaloutput of each of said second plurality of memory components in aone-to-one correspondence.
 2. A computer memory in accordance with claim1, wherein a capacitive load associated with each of said first andsecond data outputs is equal to a capacitive load associated with eachsaid first and second timing signal outputs.
 3. A computer memory inaccordance with claim 1, wherein a ratio of a number of first dataoutputs to a number of first timing signal outputs of said first moduleequals a ratio of a number of second data outputs to a number of secondtiming signal outputs of said second data module.
 4. A computer memoryin accordance with claim 1, wherein said first memory module includes adual-in-line memory module.
 5. A computer memory in accordance withclaim 1, wherein said second memory module includes a dual-in-linememory module.
 6. A computer memory in accordance with claim 1, whereineach of said first and second pluralities of memory components includesa dynamic random access memory.
 7. A computer memory in accordance withclaim 6, wherein each said first plurality of memory components includesa x8 dynamic random access memory, and each said second plurality ofmemory components includes a x16 dynamic random access memory.
 8. Acomputer memory in accordance with claim 6, wherein each of said firstplurality of memory components includes a x16 dynamic random accessmemory and each of said second plurality of memory components includes ax4 dynamic random access memory.
 9. A data processing system comprising:a first memory module including a first plurality of memory components,each of which having a plurality of first data outputs and at least afirst timing signal output; a second memory module including a secondplurality of memory components, each of which having a plurality ofsecond data outputs and at least a second timing signal output, a numberof said first plurality of memory components is different than a numberof said second plurality of memory components; a plurality of data linescoupling each of said plurality of first data outputs of each of saidfirst plurality of memory components to a respective one of each of saidplurality of second data outputs of each said second plurality of memorycomponents; and a data routing circuit of said data processing systemcoupled to each of said plurality of data lines and at least selectedones of said first and second timing signal outputs of said first andsecond memory modules, respectively, a ratio of a number of data outputsfrom said first memory module coupled to said data routing circuit to anumber of timing signal outputs from said first memory module coupled tosaid data routing circuit being equal to a ratio of a number of dataoutputs from said second memory module coupled to said data routingcircuit to a number of timing signal outputs from said second memorymodule coupled to said data routing circuit.
 10. A data processingsystem in accordance with claim 9, wherein a capacitive load associatedwith each of said first and second data outputs is equal to a capacitiveload associated with each said first and second timing signal outputs.11. A data processing system in accordance with claim 9, wherein saidfirst memory module includes a dual-in-line memory module.
 12. A dataprocessing system in accordance with claim 9, wherein said second memorymodule includes a dual-in-line memory module.
 13. A data processingsystem in accordance with claim 9, wherein each of said first and secondpluralities of memory components includes a dynamic random accessmemory.
 14. A data processing system in accordance with claim 13,wherein each said first plurality of memory components includes a x8dynamic random access memory having a single timing signal output, andeach said second plurality of memory components includes a x16 dynamicrandom access memory having two timing signal outputs.
 15. A dataprocessing system in accordance with claim 13, wherein each of saidfirst plurality of memory components includes a x16 dynamic randomaccess memory and each of said second plurality of memory componentsincludes a x4 dynamic random access memory.
 16. A method of making acomputer memory comprising the steps of: providing a first memory modulehaving a first plurality of memory components, each of which having aplurality of first data outputs and at least one timing signal output;providing a second memory module having a second plurality of memorycomponents, each of which having a plurality of second data outputs andat least one timing signal output, a number of said first plurality ofmemory components is different than a number of said second plurality ofmemory components; coupling each of said plurality of first data outputsof each of said first plurality of memory components to a respective oneof each of said plurality of second data outputs of each said secondplurality of memory components; and coupling each of said at least onetiming signal output of each of said first plurality of memorycomponents to a respective one of said at least one timing signal outputof each of said second plurality of memory components, whereby acapacitive load associated with each of said first and second dataoutputs is equal to a capacitive load associated with each said firstand second timing signal outputs.
 17. A method in accordance with claim16, wherein said first memory module includes a dual-in-line memorymodule.
 18. A method in accordance with claim 16, wherein said secondmemory module includes a dual-in-line memory module.
 19. A method inaccordance with claim 16, wherein each of said first and secondpluralities of memory components includes a dynamic random accessmemory.
 20. A method in accordance with claim 19, wherein each saidfirst plurality of memory components includes a x8 dynamic random accessmemory, and each said second plurality of memory components includes ax16 dynamic random access memory.
 21. A method in accordance with claim19, wherein each of said first plurality of memory components includes ax16 dynamic random access memory and each of said second plurality ofmemory components includes a x4 dynamic random access memory.
 22. Amethod in accordance with claim 16, wherein a ratio of a number of firstdata outputs to a number of first timing signal outputs equals a ratioof a number of second data outputs to a number of second timing signaloutputs.
 23. A dynamic random access memory (DRAM) arranged on a singleintegrated circuit, the DRAM having a plurality of clock outputs and aplurality of data outputs, a portion of the plurality of clock outputsbeing used to synchronously transfer a portion of the plurality of dataoutputs.
 24. A memory comprising: a memory module including a pluralityof dynamic random access memory (DRAM) integrated circuits; and aplurality of clock outputs extending from the memory module forsynchronously transferring data from the memory module, a number of theplurality of clock outputs being greater than a number of DRAM circuitsin the module.
 25. The memory of claim 24, wherein each of the pluralityof clock outputs extending from the memory module are coupled to a clockoutput of one of the DRAMs, each said clock output of the DRAMs beingconnected to no more than one clock output from the memory module. 26.The memory of claim 24, wherein the memory module further includes aplurality of data outputs, the data outputs coupling the memory moduleto a data routing circuit.
 27. The memory of claim 26, said memoryfurther comprising a second memory module wherein said plurality ofclock outputs is a first plurality of clock outputs and said pluralityof DRAMs is a first plurality of DRAMs, a second plurality of DRAMintegrated circuits and a second plurality of clock outputs extendingfrom the second memory module for synchronously transferring data fromthe second memory module, a number of the plurality of clock outputsbeing different than a number of said second plurality of clock outputs.28. A memory according to claim 26, the memory system being coupled to acentral processing unit through the data routing circuit.
 29. A computermemory system comprising: a first memory module including a firstplurality of memory components, the first memory module having a firstplurality of clock outputs for synchronously transferring data, a numberof the first plurality of clock outputs being greater than a number ofthe first plurality of memory components; a second memory moduleincluding a second plurality of memory components, the second memorymodule having a second plurality of clock outputs for synchronouslytransferring data from the second module, a number of said secondplurality of memory components being different than a number of saidfirst plurality of memory components; and a plurality of timing signallines coupling the first plurality of clock outputs to the secondplurality of clock outputs, each of said timing signal lines couplingone of said first plurality of clock outputs to one of said secondplurality of clock outputs.
 30. The computer memory system of claim 29,wherein said first memory module is a dual-in-line memory module. 31.The computer memory system of claim 29, wherein said second memorymodule is a dual-in-line memory module.
 32. The computer memory of claim29, wherein said first and second pluralities of memory components aredynamic random access memories.
 33. The computer memory system of claim32, wherein said first plurality of memory components include a x16dynamic random access memory, and said second plurality of memorycomponents include a x8 dynamic random access memory.
 34. The computermemory system of claim 32, wherein said first plurality of memorycomponents include a x8 dynamic random access memory, and said secondplurality of memory components include a x4 dynamic random accessmemory.
 35. The computer system of claim 29, wherein each memorycomponent in each said first and second pluralities of memory componentshaving at least one timing signal output, each of said clock outputs isconnected to a respective one of said timing outputs.
 36. The computersystem of claim 29, wherein the first memory module further comprises aplurality of first data outputs and the second memory module furthercomprises a plurality of second data outputs; and the computer systemfurther comprises a plurality of data lines coupling each of saidplurality of first data outputs to a respective one of each of saidplurality of second data outputs.
 37. The computer system of claim 36,wherein the plurality of data lines are further coupled to data inputsof an integrated circuit for transferring data transmitted over theplurality of data lines to a computer bus.
 38. The computer memorysystem of claim 37, wherein the plurality of timing signal lines arefurther coupled to clock-inputs of the integrated circuit forsynchronously transferring the data.
 39. A memory module comprising: aplurality of data storage devices; and a plurality of timing signaloutput lines extending from the plurality of data storage devices,selected ones of said plurality of timing signal output lines extendingbeyond said module, each said selected ones of said plurality of timingsignal output lines connected to a different clock output of saidplurality of data storage devices, and a number of said timing signaloutput lines extending from the data storage devices being greater thana number of said plurality of storage devices.
 40. A memory module inaccordance with claim 39, wherein each of said plurality of data storagedevices comprises a dynamic random access memory.
 41. A memory module inaccordance with claim 39, wherein each of said plurality of data storagedevices comprises a synchronous dynamic random access memory.
 42. Amemory module in accordance with claim 39, wherein said timing signaloutputs extending from the memory module are first memory moduleoutputs, said memory module further comprising: a plurality of datalines within said module, each of said plurality of data lines connectedto a respective data output of said plurality of data storage devices;and a plurality of second memory module outputs, each of said pluralityof second memory module outputs connected to a respective one of saidplurality of data lines.